This invention relates to semiconductor memory devices and, more particularly, to modification of integrated circuit memories, such as Dynamic Random Access Memories (DRAMs), to become universal modular memories.
In general, semiconductor memory devices, such as DRAMs, are formed from sub-arrays, or modules, of memory cells. For example, a four-megabit DRAM may be formed on a chip using four modules, each module including one million memory cells.
The memory cells of each array module are formed in rows and columns. Each memory cell in a row is connected to a conductive row line and each memory cell in a column is connected to at least one conductive column line. Row addresses are applied to the row lines and column addresses are applied to the column lines for the purpose of storing and reading digital data in the memory cells and, in the case of DRAMs, refreshing the memory cells. The digital data are sensed by sense amplifiers connected to the column lines of each module.
The number of row address bits received by a DRAM from a microprocessor may, by industry standard, be equal to the number of column address bits. For example, the row address signals and the column address signals furnished by a microprocessor to a four-megabit DRAM may each have 11 bits. However, the information from the column address bits and from the row address bits may be redefined to conform to the array module configuration. In redefining the bits, one or more of the row bits may be assigned to address one or more columns in a module or modules of cells. Similarly, one or more of the column bits or the row bits may be assigned to designate a particular module in which data may be stored or read. For example, one row bit may designate whether a top module or a bottom module is being read. One column bit may designate whether a left module or a right module is being read.
Modular DRAMs (MODRAMs) are DRAMs that, because of manufacturing defects, have one or more modules that are defective. DRAMs are tested at the wafer stage of manufacture to identify which module or modules of the DRAM are functional and which are defective. Because of the random nature of defects, the functional modules of a MODRAM may assume many possible configurations, dependent on which module or modules of the array are defective. For example, either the top module(s) or the bottom module(s) may be functional. In other cases either the left module(s) or the right module(s) may be functional. However, system designers generally must specify address and pin connections for circuit systems using MODRAMs. In the past, this has meant that MODRAMs must be categorized and sold, for example, as top-array-module functional only or as bottom-array-module functional only. Therefore, a designer could design a particular system to use only one or the other of the categories because the DRAM assigned pin address may, for example, be RA10=0 for top module or modules and, using the same example, pin address RA10=1 may be assigned to the bottom module or modules of the DRAM.
There is a need for a universal memory circuit comprised of functional modules at a variety of locations, yet the memory circuit is alterable to have the same pin-address specification regardless of the variety of locations.